Semiconductor device package and method for fabricating the same

ABSTRACT

A semiconductor device package includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the first portion is inserted into the first interposer hole.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2017-0053633, filed on Apr. 26, 2017,and entitled, “Semiconductor Device Package and Method for Fabricatingthe Same,” is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

One or more embodiments described herein relate to a semiconductordevice package and a method for fabricating a semiconductor devicepackage.

2. Description of the Related Art

Reducing the size of electronic devices continues to be a goal of systemdesigners. One way to reduce the size of electronic devices to reducethe thickness of the semiconductor device packages in those devices.Reducing the thickness of semiconductor device packages raises issues ofeffective dissipation of heat generated from semiconductor chips inthose packages.

SUMMARY

In accordance with one or more embodiments, a semiconductor devicepackage includes a first semiconductor package including a firstsemiconductor package substrate and a first semiconductor chip; a secondsemiconductor package including a second semiconductor package substrateand a second semiconductor chip; and an interposer between the firstsemiconductor package and the second semiconductor package toelectrically connect the first semiconductor package to the secondsemiconductor package, wherein the interposer includes a firstinterposer hole passing through the interposer and wherein the firstsemiconductor chip includes a first portion and a second portion whichprotrudes from the first portion and which is inserted into the firstinterposer hole.

In accordance with one or more other embodiments, a semiconductor devicepackage includes a first semiconductor package including a firstsemiconductor package substrate and a first semiconductor chip includinga first portion and a second portion protruding from the first portion;a second semiconductor package including a second semiconductor packagesubstrate and a second semiconductor chip; an interposer between thefirst semiconductor package and the second semiconductor package, theinterposer including a first interposer hole exposing the secondportion, the interposer including a first surface facing a secondsurface; and a connector on the first surface of the interposer, whereina width of the first portion is larger than a width of the secondportion and wherein a part of the first portion overlaps the connector.

In accordance with one or more other embodiments, an apparatus includesa first semiconductor package; a second semiconductor package; and aninterposer to electrically connect the first semiconductor package tothe second semiconductor package, wherein the interposer includes a holeand wherein a first portion of a semiconductor chip in the firstsemiconductor package is in the hole and extends in a direction of thesecond semiconductor package.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describingin detail exemplary embodiments with reference to the attached drawingsin which:

FIGS. 1 to 24 illustrate embodiments of a semiconductor device package;and

FIGS. 25A to 25D, 26A, 26B, 27A to 27C, 28A to 28D, 29A and 29Billustrate stages in embodiments of a method for fabricating asemiconductor device package.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a semiconductor device package.FIGS. 2A and 2B illustrate cross-sectional views taken along line A-A′in FIG. 1 according to one or more embodiments. FIG. 2C illustrates anenlarged view of an embodiment of region k in FIG. 2A. FIG. 3illustrates an embodiment of a semiconductor chip in a semiconductordevice package. FIGS. 4A to 4C illustrate cross-sectional views takenalong line A-A′ in FIG. 1 according to some embodiments.

FIG. 1 illustrates an embodiment of a partial area of a substrate 10 onwhich a plurality of semiconductor packages is to be mounted. In FIG. 1,only the substrate 10 and an interposer 300 are shown for clarity ofillustration. In FIGS. 2A, 2B, and 4A to 4C, the substrate 10 is notshown for clarity of illustration.

Referring to FIGS. 1 and 2A, a semiconductor device package according tosome embodiments may include a first semiconductor package 100 and asecond semiconductor package 200, and the interposer 300 is on thesubstrate 10. The first semiconductor package 100 may be on thesubstrate 10. The first semiconductor package 100 may include a firstsemiconductor package substrate 101, a first semiconductor chip 110, anda first molding material 120.

The first semiconductor package substrate 101 may be a substrate for apackage, for example, a printed circuit board (PCB) or a ceramicsubstrate. The first semiconductor package substrate 101 may includefirst and second surfaces facing each other. The first semiconductorchip 110 may be mounted on the first surface of the first semiconductorpackage substrate 101. A first connection element (e.g., connector) 103may be attached to the second surface of the first semiconductor packagesubstrate 101. A predetermined number of the first connection elements(or connectors) 103 are illustrated. A different number of the firstconnection elements 103 may be attached to the second surface of thefirst semiconductor package substrate 101 in another embodiment.

The first connection element 103 may be, for example, a conductive ballor a solder ball. For example, the first connection element 103 may beone of a conductive bump, a conductive spacer, and a pin grid array(PGA). The first semiconductor package 100 may be electrically connectedto an external device through the first connection element 103.

The first semiconductor chip 110 may be, for example, a flip chip. Thelower surface of the first semiconductor chip 110 may be a firstsemiconductor device circuit region 111. A second connection element 113may be in the first semiconductor device circuit region 111. The secondconnection element 113 may be, for example, a solder ball or aconductive bump.

The first semiconductor chip 110 may be electrically connected to thefirst semiconductor package substrate 101 through the second connectionelement 113. A predetermined number of the second connection elements113 are illustrated. A different number of the second connectionelements 113 may be included in other embodiments.

Referring to FIGS. 1, 2A, and 3, the shape of the first semiconductorchip 110 may be, for example, a stepped shape. In some embodiments, thewidth W1 of a first portion 110_1 may be larger than a width W2 of asecond portion 110_2. The first semiconductor chip 110 may include thefirst portion 110_1 and the second portion 110_2. The second portion110_2 may protrude from the first portion 110_1. In some embodiments,the first portion 110_1 may include, for example, the firstsemiconductor device circuit region 111. In some embodiments, The firstportion 110_1 and the second portion 110_2 may be connected to eachother.

Each of the first portion 110_1 and the second portion 110_2 may be aportion of one first semiconductor chip 110. In one embodiment, thefirst portion 110_1 and the second portion 110_2 may be differentsemiconductor chips. In one embodiment, the first semiconductor chip 110may include two different semiconductor chips.

The shape of the first semiconductor chip 110 may be different from thatillustrated in FIG. 2A. For example, referring to FIG. 2B, the shape ofa first semiconductor chip 110′ may not have any steps. A first′ portion110′_1 of the first semiconductor chip 110′ may be a portion notinserted into a first interposer hole 300 h_1. A second portion 110′_2of the first′ semiconductor chip 110′ may be inserted into the firstinterposer hole 300 h_1. The first semiconductor chip 110′ may be onesemiconductor chip, or in another embodiment a stack of a plurality ofsemiconductor chips may be included.

Referring again to FIGS. 1 and 2A, the first molding material 120 mayinclude a hole 310 h for receiving a third connection element 310. Thefirst molding material 120 may completely fill a space between the firstsemiconductor chip 110 and the first semiconductor package substrate101. The first molding material 120 may completely surround the sidesurface of the first portion 110_1 and the side surface of the thirdconnection element 310. The first molding material 120 may completelyfill, for example, a space between the upper surface of the firstportion 110_1 of the first semiconductor chip and the interposer 300.

The first molding material 120 may surround only a part of the sidesurface of the second portion 110_2, for example. In one embodiment, thefirst molding material 120 may completely fill the space between theupper surface of the first portion 110_1 and the interposer 300, but maynot contact the side surface of the second portion 110_2. Accordingly,an empty space may be between the side surface of the second portion110_2 and the first molding material 120. The first molding material 120may be, for example, an epoxy molding compound (EMC).

The second semiconductor package 200 may be on the substrate 10 and mayinclude a second semiconductor package substrate 201, a secondsemiconductor chip 210, and a second molding material 220.

The second semiconductor package substrate 201 may be the same as ordifferent from the first semiconductor package substrate 101. The secondsemiconductor package substrate 201 may include first and secondsurfaces facing each other. The second semiconductor chip 210 may bemounted on the first surface of the second semiconductor packagesubstrate 201. A fourth connection element 203 may be attached to thesecond surface of the second semiconductor package substrate 201. Thefourth connection element 203 may be the same as or different from thefirst connection element 103. The second semiconductor package 200 maybe electrically connected to an external device or another semiconductorpackage through the fourth connection element 203.

The second semiconductor chip 210 may be attached to the secondsemiconductor package substrate 201 through a first adhesive 215. Thesecond semiconductor chip 210 may be electrically connected to thesecond semiconductor package substrate 201 through a fifth connectionelement 213, for example. The upper surface of the second semiconductorchip 210 may be a second semiconductor device circuit region 211. Thefifth connection element 213 may be, for example, wire bonding. Thesecond semiconductor chip 210 is one semiconductor chip, or in anotherembodiment a stack of a plurality of semiconductor chips may beincluded.

Each of the first semiconductor chip 110 and the second semiconductorchip 210 may be, for example, a memory chip, a logic chip, or anothertype of church. When the first semiconductor chip 110 and/or the secondsemiconductor chip 210 is a logic chip, the first semiconductor chip 110and/or the second semiconductor chip 210 may be variously designed inconsideration of operations to be performed. When the firstsemiconductor chip 110 and/or the second semiconductor 202 is a memorychip, the memory chip may be, for example, a non-volatile memory chip.

The second molding material 220 may be on the second semiconductorpackage substrate 201. The second molding material 220 may seal theupper surface of the second semiconductor package substrate 201, thesecond semiconductor chip 210, and the fifth connection element 213. Thesecond molding material 220 may include, for example, the same materialas the first molding material 120.

The interposer 300 may be between the first semiconductor package 100and the second semiconductor package 200. The interposer 300 mayelectrically connect the first semiconductor package 100 to the secondsemiconductor package 200. The interposer 300 may include first andsecond surfaces facing each other. A connection element of thesemiconductor package on the interposer 300 may be on the first surfaceof the interposer 300. The third connection element 310 may be attachedto the second surface of the interposer 300. The interposer 300 mayinclude the first interposer hole 300 h_1 passing through the interposer300. The first interposer hole 300 h_1 may extend from the first surfaceto the second surface of the interposer 300.

In some embodiments, the second semiconductor package 200 may be on thefirst semiconductor package 100. For example, the first semiconductorpackage 100 and the second semiconductor package 200 may have a Packageon Package (PoP) structure. The first portion 110_1 of the firstsemiconductor chip 110 may be between the second portion 110_2 and thefirst semiconductor package substrate 101. The interposer 300 may bebetween the first semiconductor package 100 and the second semiconductorpackage 200. The third connection element 310 may be inserted into ahole 310 h of the first molding material 120. The fourth connectionelement 203 may be on the first surface of the interposer 300. Forexample, the fourth connection element 203 may be between the firstsurface of the interposer 300 and the second semiconductor packagesubstrate 201. The fourth connection element 203 may be on a portion ofthe first surface of the interposer 300, other than a portion where thefirst interposer hole 300 h_l is formed.

The first semiconductor package substrate 101 may be electricallyconnected to the interposer 300 through the third connection element310. The interposer 300 may be electrically connected to the secondsemiconductor package substrate 201 through the fourth connectionelement 203.

The second portion 110_2 of the first semiconductor chip may be insertedinto the first interposer hole 300 h_1. For example, the firstinterposer hole 300 h_1 may expose the second portion 110_2 of the firstsemiconductor chip when viewed in a direction from the first surface ofthe interposer 300 toward the second surface of the interposer 300 as inFIG. 1.

The second portion 110_2 of the first semiconductor chip may protrudefrom the upper surface of the first surface of the interposer 300. Inone embodiment, depending on a semiconductor chip fabricating process,the second portion 110_2 may not protrude from the upper surface of thefirst surface of the interposer 300.

Referring to FIGS. 1, 2A, and 2C, a portion 110_1 a of the first portionof the first semiconductor chip may at least partially overlap afourth_first connection element 203_1. The overlapping direction may be,for example, a vertical direction with respect to the firstsemiconductor package substrate 101. For example, the fourth connectionelement 203 may include a plurality of connection elements forelectrically connecting the interposer 300 with the second semiconductorpackage 200. For example, a plurality of connection elements of thefourth connection element 203 may include the fourth_first connectionelement 203_1. The fourth_first connection element 203_1 may be aconnection element closest to the first interposer hole 300 h_1 amongthe plurality of connection elements in the fourth connection element203. The portion 110_1 a of the first portion of the first semiconductorchip may be a portion including an end portion 110_1 e of the firstportion of the first semiconductor chip. For example, the portion 110_1a of the first portion of the first semiconductor chip may not overlapthe second portion 110_2 of the first semiconductor chip.

Referring again to FIGS. 1 and 2A, an empty space may be between asidewall of the first interposer hole 300 h_1 and a sidewall of thesecond portion 110_2 of the first semiconductor chip. For example, thearea of the first interposer hole 300 h_1 may be larger than the area ofthe upper surface of the second portion 110_2 of the first semiconductorchip. Also, for example, an empty space may be between the upper surfaceof the second portion 110_2 of the first semiconductor chip and thesecond surface of the second semiconductor package substrate 201.

As shown in FIG. 4A, a fourth connection element 203′ and a pad 203 pmay be between the upper surface of the first semiconductor chip 110 andthe second surface of the second semiconductor package substrate 201.The fourth connection element 203′ may include a material (e.g., a heattransfer material) for transferring the heat of the first semiconductorpackage 100 to the outside. The pad 203 p may be, for example, a wettinglayer including an easily wettable material. The pad 203 p may be, forexample, a metal wetting layer. The first semiconductor chip 110 may bethermally connected to the second semiconductor package 200 through thefourth′ connection element 203′ and the pad 203 p on the upper surfaceof the first semiconductor chip 110.

A heat transfer material may be, for example, between the sidewall ofthe first interposer hole 300 h_1 and the sidewall of the second portion110_2 of the first semiconductor chip. Further, for example, as shown inFIG. 4B, a heat transfer material layer 400 may be further formedbetween the upper surface of the second portion 110_2 of the firstsemiconductor chip and the second surface of the second semiconductorpackage substrate 201. The heat transfer material layer 400 may be, forexample, a thermal interface material (TIM). In FIG. 4B, the heattransfer material layer 400 is formed only between the upper surface ofthe second portion 110_2 of the first semiconductor chip and the secondsurface of the second semiconductor package substrate 201.

In one embodiment, the heat transfer material layer 400 may be partiallyformed along the sidewall of the second portion 110_2 of the firstsemiconductor chip, as well as between the upper surface of the secondportion 110_2 of the first semiconductor chip and the second surface ofthe second semiconductor package substrate 201. The heat transfermaterial layer 400 may fill at least a part of the empty space betweenthe sidewall of the second portion 110_2 of the first semiconductor chipand the sidewall of the first interposer hole 300 h_l. The firstsemiconductor chip 110 may be thermally connected to the secondsemiconductor package 200 through the heat transfer material layer 400.

As shown in FIG. 4C, an insertion adhesive layer 401 may be between theheat transfer material layer 400 and the second surface of the secondsemiconductor package substrate 201.

In the semiconductor device package according to some embodiments, aportion of the first semiconductor chip 110 may be inserted into thefirst interposer hole 300 h_1 to increase the overall thickness of thefirst semiconductor chip 110. When the overall thickness of the firstsemiconductor chip 110 is increased, the heat generated from the firstsemiconductor chip 110 may be effectively transferred in a horizontaldirection. When the heat is effectively transferred in the horizontaldirection, the thermal resistance is reduced and performance of thesemiconductor device package may be improved. Further, when the heat iseffectively transferred in the horizontal direction, the temperaturedistribution inside the semiconductor chip becomes uniform. As a result,reliability of the semiconductor device package may be improved.

According to some embodiments, in the semiconductor device package, thesecond portion 110_2 of the first semiconductor chip may be insertedinto the first interposer hole 300 h_1. Accordingly, the heat generatedfrom the first semiconductor chip 110 may be effectively transferred inthe vertical direction. When the heat is effectively transferred in thevertical direction, the thermal resistance is reduced and performance ofthe semiconductor device package may be improved.

FIG. 5 illustrates another embodiment of a semiconductor device package.FIG. 6A illustrates a cross-sectional view taken along line B-B′ in FIG.5 according to one embodiment. FIG. 6B illustrates an embodiment of anenlarged view of region 1 in FIG. 6A. FIG. 7 illustrates across-sectional view taken along line B-B′ of FIG. 5 according to oneembodiment. FIG. 5 illustrates only a partial area of a substrate 10 onwhich a plurality of semiconductor packages may be mounted. In FIG. 5,only the substrate 10 and the interposer 300 are shown for clarity ofillustration.

Referring to FIGS. 5 and 6A, the first semiconductor package 100 may beon the second semiconductor package 200. The first semiconductor package100 includes the first semiconductor package substrate 101, the firstsemiconductor chip 110, the second connection element 113, a secondadhesive 115, and the first molding material 120. The firstsemiconductor package substrate 101 may include a first substrate hole101 h_1 passing through the first semiconductor package substrate 101.The first substrate hole 101 h_1 may extend from the first surface tothe second surface of the first semiconductor package substrate 101.

The upper surface of the first semiconductor chip 110 may be the firstsemiconductor device circuit region 111. The second connection element113 may be, for example, wire bonding. The first semiconductor chip 110may be electrically connected to the first semiconductor packagesubstrate 101 through the second connection element 113.

The first semiconductor chip 110 may be attached to the firstsemiconductor package substrate 101 through the second adhesive 115. Thesecond adhesive 115 may be disposed between the first portion 110_1 ofthe first semiconductor chip and the first semiconductor packagesubstrate 101.

The first molding material 120 may seal the first surface of the firstsemiconductor package substrate 101, the first semiconductor chip 110,the second connection element 113, and the second adhesive 115.

The second semiconductor package 200 may include the secondsemiconductor package substrate 201, the second semiconductor chip 210,the fifth connection element 213, and the second molding material 220.The second semiconductor chip 210 may be a flip chip. The lower surfaceof the second semiconductor chip 210 may be the second semiconductordevice circuit region 211. The fifth connection element 213 may be inthe second semiconductor device circuit region 211. The fifth connectionelement 213 may be, for example, a solder ball or a conductive bump.

The second molding material 220 may include the hole 310 h for receivingthe third connection element 310. The second molding material 220 maycompletely fill a space between the second semiconductor chip 210 andthe second semiconductor package substrate 201. The second moldingmaterial 220 may completely surround the side surface of the secondsemiconductor chip 210 and the side surface of the third connectionelement 310. The second molding material 220 may be on the upper surfaceof the second semiconductor chip 210 to cover the upper surface of thesecond semiconductor chip 210. In one embodiment, the second moldingmaterial 220 may cover only a part of the upper surface of the secondsemiconductor chip 210.

The first connection element 103 may be on the first surface of theinterposer 300. The first connection element 103 may be between thefirst surface of the interposer 300 and the first semiconductor packagesubstrate 101. The first connection element 103 may be on a portion ofthe first surface of the interposer 300 other than a portion where thefirst interposer hole 300 h_1 is formed.

The first semiconductor package substrate 101 may be electricallyconnected to the interposer 300 through the first connection element103. The interposer 300 may be electrically connected to the secondsemiconductor package substrate 201 through the third connection element310.

The first portion 110_1 of the first semiconductor chip may include thefirst semiconductor device circuit region 111. Referring to FIGS. 5, 6A,and 6B, the portion 110_1 a of the first portion of the firstsemiconductor chip may at least partially overlap the first connectionelement 103_1. The overlapping direction may be, for example, a verticaldirection with respect to the second semiconductor package substrate201.

The first connection element 103 may include, for example, a pluralityof connection elements for electrically connecting the interposer 300 tothe first semiconductor package 100. In one embodiment, a plurality ofconnection elements of the first connection element 103 may include afirst_first connection element 103_1. The first_first connection element103_1 may be a connection element closest to the first interposer hole300 h_1 and the first substrate hole 101 h_1 among the plurality ofconnection elements in the first connection element 103.

Referring again to FIGS. 5 and 6A, the width W1 of the first portion ofthe first semiconductor chip may be larger than the width W2 of thesecond portion of the first semiconductor chip. The second portion 110_2of the first semiconductor chip may be inserted into the firstinterposer hole 300 h_1 through the first substrate hole 101 h_l Thesecond portion 110_2 of the first semiconductor chip may be between thefirst portion 110_1 of the first semiconductor chip and the secondsemiconductor chip 210. The second portion 110_2 of the firstsemiconductor chip may be exposed through the first substrate hole 101h_1 and the first interposer hole 300 h_1 when viewed in a directiontoward the first surface of the interposer 300 from the second surfaceof the interposer 300. When viewed from the first surface of theinterposer 300 toward the second surface of the interposer 300, thesecond molding material 220 may be exposed as in FIG. 5.

The second portion 110_2 of the first semiconductor chip may notprotrude from the second surface of the interposer 300. An empty spacemay be between the upper surface of the second portion 110_2 of thefirst semiconductor chip and the upper surface of the second moldingmaterial 220. Further, an empty space may be between the sidewall of thesecond portion 110_2 of the first semiconductor chip and the sidewall ofthe first substrate hole 101 h _1, and between the sidewall of thesecond portion 110_2 of the first semiconductor chip and the sidewall ofthe first interposer hole 300 h_1. For example, the area of the firstinterposer hole 300 h_1 and the area of the first substrate hole 101 h_1may be larger than the area of the upper surface of the second portion110_2 of the first semiconductor chip.

In one embodiment, as shown in FIG. 7, the heat transfer material layer400 may be further formed between the upper surface of the secondportion 110_2 of the first semiconductor chip and the upper surface ofthe second molding material 220. Further, the heat transfer materiallayer 400 may fill at least a part of the empty space formed between thesidewall of the first interposer hole 300 h_1 and the sidewall of thesecond portion 110_2 of the first semiconductor chip, for example. Theheat transfer material layer 400 may further include an optionalinsertion adhesive layer.

FIG. 8A illustrates a cross-sectional view taken along line A-A′ in FIG.1 according to an embodiment. FIG. 8B illustrates an enlarged view ofregion m in FIG. 8A according to an embodiment. FIG. 9 illustrates across-sectional view taken along line A-A′ of FIG. 1 according to anembodiment.

Referring to FIGS. 1, 2A, and 8A, the second semiconductor package 200may be on the first semiconductor package 100. The semiconductor devicepackage of FIG. 2A and the semiconductor device package of FIG. 8A maybe substantially the same except for a second substrate hole 201 h andthe second portion 110_2 of the first semiconductor chip. The secondsemiconductor package substrate 201 may include a first surface on whichthe second semiconductor chip 210 is disposed and a second surface onwhich the fourth connection element 203 is attached. The first andsecond surfaces may face each other.

The second semiconductor package substrate 201 may include the secondsubstrate hole 201 h passing through the second semiconductor packagesubstrate 201. The second substrate hole 201 h may extend from the firstsurface to the second surface of the second semiconductor packagesubstrate 201. The second portion 110_2 of the first semiconductor chipmay be inserted into the second substrate hole 201 h through the firstinterposer hole 300 h_1. For example, at least a part of the secondportion 110_2 of the first semiconductor chip may be inserted into thesecond semiconductor package substrate 201.

In one embodiment, the second portion 110_2 of the first semiconductorchip may include a portion to be inserted into the first interposer hole300 h_1 and a portion to be inserted into the second substrate hole 201h. The upper surface of the second portion 110_2 of the firstsemiconductor chip may be in the portion to be inserted into the secondsubstrate hole 201 h. The upper surface of the second portion 110_2 ofthe first semiconductor chip may be below the first surface of thesecond semiconductor package substrate 201. In some embodiments, thewidth W1 of the first portion 110_1 of the first semiconductor chip maybe substantially the same as the width W2 of the second portion 110_2 ofthe first semiconductor chip. In this case, the portion to be insertedinto the first interposer hole 300 h_1 and the second substrate hole 201h may be the second portion 110_2 of the first semiconductor chip. Theremaining portion may be the first portion 110_1 of the firstsemiconductor chip.

An empty space may be between the upper surface of the second portion110_2 of the first semiconductor chip and the first adhesive 215. Also,an empty space may be between the sidewall of the second portion 110_2of the first semiconductor chip and the sidewall of the second substratehole 201 h, between the sidewall of the second portion 110_2 of thefirst semiconductor chip and the sidewall of the first interposer hole300 h_1, and between the sidewall of the second portion 110_2 of thefirst semiconductor chip and the fourth connection element 203. In oneembodiment, the pad and the fourth′ connection element (e.g., see FIG.4A) for thermally connecting the first semiconductor package 100 to thesecond semiconductor package 200 may be further disposed between theupper surface of the second portion 110_2 of the first semiconductorchip and the first adhesive 215.

Further, as shown in FIG. 9, the heat transfer material layer 400 may bebetween the upper surface of the second portion 110_2 of the firstsemiconductor chip and the first adhesive 215. The heat transfermaterial layer 400 may fill, for example, at least a part of the emptyspace between the sidewall of the second portion 110_2 of the firstsemiconductor chip and the sidewall of the second substrate hole 201 h.The heat transfer material layer 400 may further include an optionalinsertion adhesive layer.

Referring again to FIGS. 1, 2A, 8A, and 8B, the portion 110_1 a of thefirst portion of the first semiconductor chip may at least partiallyoverlap the fourth first connection element 203_1. The overlappingdirection may be, for example, a vertical direction with respect to thefirst semiconductor package substrate 101.

FIG. 10 illustrates a cross-sectional view taken along line A-A′ in FIG.1 according to another embodiment. Referring to FIGS. 1, 8A, 8B, and 10,the second semiconductor package 200 may be on the first semiconductorpackage 100. The semiconductor device package of FIG. 8A and thesemiconductor device package of FIG. 10 may be substantially the same,except for a cavity 201 c. For example, as compared with the secondsemiconductor package substrate 201 of FIG. 8A, the second semiconductorpackage substrate 201 of FIG. 10 may include the cavity 201 c instead ofthe second substrate hole 201 h. The cavity 201 c may not pass throughthe second semiconductor package substrate 201. The cavity 201 c may beformed by removing a part of the second surface of the secondsemiconductor package substrate 201.

The second portion 110_2 of the first semiconductor chip may be insertedinto the cavity 201 c through the first interposer hole 300 h_1. Thesecond portion 110_2 of the first semiconductor chip may include aportion to be inserted into the first interposer hole 300 h_1 and aportion to be inserted into the cavity 201 c. The upper surface of thesecond portion 110_2 of the first semiconductor chip may be in theportion to be inserted into the cavity 201 c. In some embodiments, thewidth W1 of the first portion 110_1 of the first semiconductor chip maybe substantially the same as the width W2 of the second portion 110_2 ofthe first semiconductor chip. In this case, the portion to be insertedinto the first interposer hole 300 h_1 and the cavity 201 c may be thesecond portion 110_2 of the first semiconductor chip. The remainingportion of the first semiconductor chip may be the first portion 110_1of the first semiconductor chip.

An empty space may be between the upper surface of the second portion110_2 of the first semiconductor chip and the cavity 201 c. In oneembodiment, one of the heat transfer material layer (e.g., see FIG. 4B)and the fourth connection element (e.g., see FIG. 4A) may be in an emptyspace between the upper surface of the second portion 110_2 of the firstsemiconductor chip and the cavity 201 c. As a result, the firstsemiconductor package 100 may be thermally connected to the secondsemiconductor package 200. When the fourth connection element is in theempty space between the upper surface of the second portion 110_2 of thefirst semiconductor chip and the cavity 201 c, a pad (e.g., a wettinglayer) may be between the fourth connection element and the uppersurface of the second portion 110_2 of the first semiconductor chip.

In the semiconductor device package according to some embodiments, heatdissipation generated from the first semiconductor chip 110 and the likemay be effective as described above. In addition, by forming the secondsubstrate hole 201 h or the cavity 201 c in the second semiconductorpackage substrate 201 of the second semiconductor package 200 on thefirst semiconductor package 100, the chances of warpage may be reduced.

FIG. 11A illustrates a cross-sectional view taken along line A-A′ inFIG. 1 according to an embodiment. FIG. 11B illustrates an enlarged viewof region n in FIG. 11A according to an embodiment. FIG. 12 illustratescross-sectional view taken along line A-A′ of FIG. 1 according to anembodiment.

Referring to FIGS. 1 and 11A, the second semiconductor package 200 maybe on the first semiconductor package 100. The first semiconductorpackage 100 of FIG. 11A may be substantially the same as the firstsemiconductor package 100 of FIG. 2A. In some embodiments, the width W1of the first portion 110_1 of the first semiconductor chip may besubstantially the same as the width W2 of the second portion 110_2 ofthe first semiconductor chip. In this case, the portion to be insertedinto the first interposer hole 300 h_1 may be the second portion 110_2of the first semiconductor chip. The remaining portion of the firstsemiconductor chip may be the first portion 110_1 of the firstsemiconductor chip.

The second semiconductor package 200 may include the secondsemiconductor package substrate 201, the second semiconductor chip 210,the fifth connection element 213, the first adhesive 215, and the secondmolding material 220. The second semiconductor package substrate 201including the second substrate hole 201 h of FIG. 11A may besubstantially the same as the second semiconductor package substrate 201of FIG. 8A.

The second semiconductor chip 210 may have, for example, a steppedshape. The second semiconductor chip 210 may include a third portion210_1 and a fourth portion 210_2. The fourth portion 210_2 of the secondsemiconductor chip may protrude from the third portion 210_1 of thesecond semiconductor chip. The third portion 210_1 of the secondsemiconductor chip may include, for example, the second semiconductordevice circuit region 211. The third portion 210_1 and the fourthportion 210_2 of the second semiconductor chip may be connected to eachother.

Each of the third portion 210_1 and the fourth portion 210_2 of thesecond semiconductor chip are illustrated to be a part of one secondsemiconductor chip 210. In one embodiment, the third portion 210_1 andthe fourth portion 210_2 of the second semiconductor chip may bedifferent semiconductor chips, respectively. In one embodiment, thesecond semiconductor chip 210 may be replaced, for example, by twodifferent semiconductor chips. The width W3 of the third portion 210_1of the second semiconductor chip may be different from (e.g., largerthan) the width W4 of the fourth portion 210_2 of the secondsemiconductor chip.

The second semiconductor chip 210 may be electrically connected to thesecond semiconductor package substrate 201 through the fifth connectionelement 213. The fifth connecting element 213 may be, for example, wirebonding. The second semiconductor chip 210 may be electrically connectedto the second semiconductor package substrate 201, for example, throughthe first adhesive 215. The first adhesive 215 may be between the thirdportion 210_1 of the second semiconductor chip and the secondsemiconductor package substrate 201.

The fourth portion 210_2 of the second semiconductor chip may beinserted into the second substrate hole 201 h. The upper surface of thefourth portion 210_2 of the second semiconductor chip may face the uppersurface of the second portion 110_2 of the first semiconductor chipinserted in the first interposer hole 300 h_1. The second portion 110_2of the first semiconductor chip may be disposed between the fourthportion 210_2 of the second semiconductor chip and the first portion110_1 of the first semiconductor chip.

An empty space may be between the upper surface of the fourth portion210_2 of the second semiconductor chip and the upper surface of thesecond portion 110_2 of the first semiconductor chip inserted in thefirst interposer hole 300 h_1. Further, an empty space may be betweenthe sidewall of the fourth portion 210_2 of the second semiconductorchip and the sidewall of the second substrate hole 201 h.

As shown in FIG. 12, in one embodiment, the heat transfer material layer400 may be between the upper surface of the fourth portion 210_2 of thesecond semiconductor chip and the upper surface of the second portion110_2 of the first semiconductor chip inserted in the first interposerhole 300 h_1. The heat transfer material layer 400 is illustrated to beonly between the upper surface of the fourth portion 210_2 of the secondsemiconductor chip and the upper surface of the second portion 110_2 ofthe first semiconductor chip inserted in the first interposer hole 300h_1. In one embodiment, the heat transfer material layer 400 may fill atleast a part of the empty space between the sidewall of the fourthportion 210_2 of the second semiconductor chip and the sidewall of thesecond substrate hole 201 h.

Also, the heat transfer material layer 400 may, for example, fill atleast a part of the empty space between the sidewall of the secondportion 110_2 of the first semiconductor chip and the sidewall of thefirst interposer hole 300 h_1. In some embodiments, the pad and thefourth connection element (e.g., see FIG. 4A) for thermally connectingthe first semiconductor package 100 to the second semiconductor package200 may be between the upper surface of the fourth portion 210_2 of thesecond semiconductor chip and the upper surface of the second portion110_2 of the first semiconductor chip. The pad may be between the fourthconnection element and the upper surface of the fourth portion 210_2 ofthe second semiconductor chip, and between the fourth connection elementand the upper surface of the second portion 110_2 of the firstsemiconductor chip.

Referring again to FIGS. 1, 11A, and 11B, the portion 110_1 a of thefirst portion of the first semiconductor chip and a portion 210_1 a ofthe third portion of the second semiconductor chip may at leastpartially overlap a fourth_first connection element 203_1. Theoverlapping direction may be, for example, a vertical direction withrespect to the first semiconductor package substrate 101. The portion210_1 a of the third portion of the second semiconductor chip mayinclude an end portion 210_1 e of the third portion 210_1 of the secondsemiconductor chip.

FIG. 13 illustrates another embodiment of a semiconductor devicepackage. FIG. 14 illustrates a cross-sectional view taken along lineC-C′ in FIG. 13 according to one embodiment. FIG. 13 illustrates anembodiment of only a partial area of the substrate 10 on which aplurality of semiconductor packages may be mounted. In FIG. 13, only thesubstrate 10 and the interposer 300 are shown for clarity ofillustration.

Referring to FIGS. 2A, 2C, 13, and 14, the interposer 300 may include afirst region (region 1) and a second region (region 2). The interposer300 may be on the first semiconductor package substrate 101. The firstregion and the second region of the interposer 300 may be regions spacedapart from each other. The first region may be a region where more heatis generated due to a semiconductor chip than the second region. Thefirst region of the interposer 300 may include the first interposer hole300 h_1. The second region of the interposer 300 may not include a holepassing through the second region of the interposer 300.

The first region of the interposer 300 may include a second connectionelement 113, a first semiconductor chip 110, and a first interposer hole300 h_1. The second connection element 113 and the first semiconductorchip 110 may be substantially the same as the second connecting element113 and the first semiconductor chip 110 in FIG. 2A. The second portion110_2 of the first semiconductor chip may be inserted into the firstinterposer hole 300 h 1. The first interposer hole 300 h 1 may exposethe second portion 110_2 of the first semiconductor chip. When anothersemiconductor package is on the interposer 300, one (e.g., the fourthconnection element 203_1 in FIG. 2C) of the connection elements of thesemiconductor package may overlap a portion (e.g., the portion 110_1 aof the first portion of the first semiconductor chip of FIG. 2C) of thefirst portion 110_1 of the first semiconductor chip.

In some embodiments, the width W1 of the first portion 110_1 of thefirst semiconductor chip may be substantially the same as the width W2of the second portion 110_2 of the first semiconductor chip. In thiscase, the portion to be inserted into the first interposer hole 300 h_lmay be the second portion 110_2 of the first semiconductor chip. Theremaining portion of the first semiconductor chip may be the firstportion 110_1 of the first semiconductor chip.

The second region of the interposer 300 may include a thirdsemiconductor chip 510 and a sixth connection element 513. The thirdsemiconductor chip 510 may be on the first semiconductor packagesubstrate 101 and spaced apart from the first semiconductor chip 110.The third semiconductor chip 510 may be a flip chip. The lower surfaceof the third semiconductor chip 510 may be a third semiconductor devicecircuit region 511. The sixth connection element 513 may be in the thirdsemiconductor device circuit region 511. The sixth connection element513 may be, for example, a solder ball or a conductive bump.

The third semiconductor chip 510 may be electrically connected to thefirst semiconductor package substrate 101 through the sixth connectionelement 513. A predetermined number of the sixth connection elements 513are illustrated. In another embodiment, a different number of the sixthconnection elements 513 may be provided.

A part of the third semiconductor chip 510 may not be inserted into theinterposer 300. The interposer 300 may not expose the thirdsemiconductor chip 510. The third semiconductor chip 510 may be betweenthe interposer 300 and the first semiconductor package substrate 101 andsurrounded by the first molding material 120. A predetermined number ofthe third connection elements 310 are illustrated. In one anotherembodiment, a different number of the third connection elements 310 maybe provided. In various embodiments, different types of othersemiconductor packages may be on the first semiconductor package 100.

In the semiconductor device package according to some embodiments, aninterposer hole (e.g., the first interposer hole 300 h_1) may beselectively formed in a portion of the interposer 300 that generatesmore heat than the surrounding areas to promote heat transfer in thevertical and horizontal directions.

FIG. 15 illustrates a cross-sectional view taken along line C-C′ in FIG.13. Referring to FIGS. 2A, 13, 14, and 15, the first semiconductorpackage substrate 101 may include a first substrate cavity 101 c_1 and asecond substrate cavity 101 c_2 which are spaced apart from each other.The first substrate cavity 101 c_1 and the second substrate cavity 101c_2 may be formed by removing a part of the first semiconductor packagesubstrate 101. The first substrate cavity 101 c_1 may be in the firstregion (region 1) of the interposer 300. The second substrate cavity 101c_2 may be in the second region (region 2) of the interposer 300. Thefirst semiconductor chip 110 may be substantially the same as the firstsemiconductor chip 110 in FIGS. 2A and 14. In one embodiment, the firstportion 110_1 of the first semiconductor chip may be in the firstsubstrate cavity 101 c_1 and the second portion 110_2 of the firstsemiconductor chip may be inserted into the first interposer hole 300h_1. The third semiconductor chip 510 may be substantially the same asthe third semiconductor chip 510 in FIG. 14. In one embodiment, thethird semiconductor chip 510 may be in the second substrate cavity 101c_2.

In some embodiments, the width W1 of the first portion 110_1 of thefirst semiconductor chip may be substantially the same as the width W2of the second portion 110_2 of the first semiconductor chip. In thiscase, the portion to be inserted into the first interposer hole 300 h_1may be the second portion 110_2 of the first semiconductor chip, and theportion in the first substrate cavity 101 c_1 may be the first portion110_1 of the first semiconductor chip. In one embodiment, various typesof other semiconductor packages may be disposed on the firstsemiconductor package 100.

FIG. 16 illustrates a cross-sectional view taken along line C-C′ in FIG.13 according to one embodiment. In FIG. 16, the substrate 10 is notshown for clarity of illustration. Also, in FIG. 16, the firstsemiconductor package 100 and other semiconductor packages that may bedisposed on a third semiconductor package 500 are not shown for clarityof illustration.

Referring to FIGS. 2A, 6A, 13, and 16, the first semiconductor package100 may be in the first region (region 1) of the interposer 300, and thethird semiconductor package 500 may be in the second region (region 2)of the interposer 300. The first semiconductor package 100 may besubstantially the same as the first semiconductor package 100 of FIG.2A. The third semiconductor package 500 may be substantially the same asthe second semiconductor package 200 of FIG. 6A.

In some embodiments, the width W1 of the first portion 110_1 of thefirst semiconductor chip may be substantially the same as the width W2of the second portion 110_2 of the first semiconductor chip. In thiscase, the portion to be inserted into the first interposer hole 300 h_11may be the second portion 110_2 of the first semiconductor chip. Theremaining portion of the first semiconductor chip may be the firstportion 110_1 of the first semiconductor chip.

The first semiconductor package 100 and the third semiconductor package500 may share the interposer 300. In other embodiments, various types ofother semiconductor packages may be on the first semiconductor package100 and the third semiconductor package 500.

FIG. 17 illustrates another embodiment of a semiconductor devicepackage. FIG. 18 illustrates a cross-sectional view taken along lineD-D′ in FIG. 17 according to one embodiment. FIG. 19 is a perspectiveview of a first semiconductor chip 110 of FIG. 17, which is aperspective view of a semiconductor chip in a semiconductor devicepackage according to some embodiments.

FIG. 17 illustrates only a partial area of the substrate 10 on which aplurality of semiconductor packages may be mounted according to oneembodiment. In FIG. 17, only the substrate 10 and the interposer 300 areshown for clarity of illustration. In FIG. 18, the substrate 10 andother semiconductor packages that may be on the first semiconductorpackage 100 are not shown for clarity of illustration.

Referring to FIGS. 17, 18, and 19, the first semiconductor chip 110 mayfurther include a fifth portion 110_3 which is spaced apart from thesecond portion 110_2, and protrudes from the first portion 110_1. Thefirst portion 110_1 of the first semiconductor chip may include thefirst semiconductor device circuit region 111. The width W5 of the fifthportion 110_3 of the first semiconductor chip may be less than the widthW1 of the first portion 110_1 of the first semiconductor chip.

The interposer 300 may further include a second interposer hole 300 h_2spaced apart from the first interposer hole 300 h_1. The secondinterposer hole 300 h_2 may pass through the interposer 300. The fifthportion 110_3 of the first semiconductor chip may be inserted into thesecond interposer hole 300 h_2. For example, the second interposer hole300 h_2 may expose the fifth portion 110_3 of the first semiconductorchip. In one embodiment, various types of other semiconductor packagesmay be on the first semiconductor package 100.

FIG. 20 illustrates another embodiment of a semiconductor devicepackage. FIG. 21 is a cross-sectional view taken along line E-E′ in FIG.20 according to one embodiment. FIG. 20 illustrates only a partial areaof the substrate 10 on which a plurality of semiconductor packages maybe mounted according to one embodiment. In FIG. 20, only the substrate10 and the interposer 300 are shown for clarity of illustration. In FIG.21, the substrate 10 and other semiconductor packages that may be underthe first semiconductor package 100 are not shown for clarity ofillustration.

Referring to FIGS. 6A, 14, 20 and 21, the first semiconductor packagesubstrate 101 may be on the interposer 300. The first region (region 1)of the interposer 300 may include the first semiconductor packagesubstrate 101 including the second connection element 113, the firstsemiconductor chip 110 and the first substrate hole 101 h_1, and thefirst interposer hole 300 h_1. The first semiconductor package substrate101 including the second connection element 113, the first semiconductorchip 110 and the first substrate hole 101 h_1 may be substantially thesame as that in FIG. 6A.

The second region (region 2) of the interposer 300 may include the thirdsemiconductor chip 510 and the sixth connection element 513. The thirdsemiconductor chip 510 and the sixth connection element 513 may besubstantially the same as those in FIG. 14. Various types of othersemiconductor packages may be under the first semiconductor package 100in at least one embodiment.

FIG. 22 illustrates a cross-sectional view taken along line E-E′ in FIG.20 according to one embodiment. In FIG. 22, the substrate 10 is notshown for clarity of illustration. Also, in FIG. 22, other semiconductorpackages that may be under the interposer 300 are not shown for clarityof illustration.

Referring to FIGS. 6A, 20, and 22, the first semiconductor package 100may in the first region (region 1) of the interposer 300 and the thirdsemiconductor package 500 may be in the second region (region 2) of theinterposer 300. The first semiconductor package 100 and the thirdsemiconductor package 500 may share the interposer 300.

The first semiconductor package 100 may be substantially the same as thefirst semiconductor package 100 of FIG. 6A. The third semiconductorpackage 500 may be substantially the same as the second semiconductorpackage 200 of FIG. 6A. Unlike the first molding material 120 of FIG.6A, the first molding material 120 of FIG. 22 may not include the hole310 h for receiving the third connection element 310. Various types ofother semiconductor packages may be under the first semiconductorpackage 100 and the third semiconductor package 500 according to oneembodiment.

FIG. 23 illustrates another embodiment of a semiconductor devicepackage. FIG. 24 illustrates a cross-sectional view taken along lineF-F′ in FIG. 23 according to one embodiment. FIG. 23 is a view showingonly a partial area of the substrate 10 on which a plurality ofsemiconductor packages can be mounted. In FIG. 23, only the substrate 10and the interposer 300 are shown for clarity of illustration. In FIG.24, other semiconductor packages that may be disposed under theinterposer 300 are not shown for clarity of illustration.

Referring to FIGS. 23 and 24, the first semiconductor chip 110 mayfurther include the fifth portion 110_3 which is spaced apart from thesecond portion 110_2 and protrudes from the first portion 110_1. Thefirst portion 110_1 of the first semiconductor chip may include thefirst semiconductor device circuit region 111. The width W5 of the fifthportion 110_3 of the first semiconductor chip may be less than the widthW1 of the first portion 110_1 of the first semiconductor chip.

The interposer 300 may further include the second interposer hole 300h_2 spaced apart from the first interposer hole 300 h_1. The secondinterposer hole 300 h 2 may pass through the interposer 300. The fifthportion 110_3 of the first semiconductor chip may be inserted into thesecond interposer hole 300 h_2. For example, the second interposer hole300 h_2 may expose the fifth portion 110_3 of the first semiconductorchip. Various types of other semiconductor packages may be under thefirst semiconductor package 100 according to an embodiment.

FIGS. 25A to 25D illustrate stages of an embodiment of a method forfabricating a semiconductor device package. FIGS. 25A to 25D illustratea method for forming the first semiconductor chip 110 (e.g., the firstsemiconductor chip 110 of FIG. 3) and the second semiconductor chip 210(e.g., the second semiconductor chip 210 of FIG. 11A) according to someembodiments.

Referring to FIG. 25A, a wafer 1000 may include a first surface 1000_1and a second surface 1000_2 facing each other. A first tape 1300 may beattached on the second surface 1000_2 of the wafer.

Referring to FIG. 25B, a part of the first surface 1000_1 of the wafermay be removed to form a plurality of recesses which are spaced apartfrom each other. The plurality of recesses may include a first recess r1and a second recess r2. The first recess r1 and the second recess r2 areillustrated to have a rectangular shape, but may have a different shapein another embodiment. For example, depending on the shape of a bladeused in a process, the first recess r1 and the second recess r2 may havea round shape. Depending on the shape of the blade used in the process,the sidewall of each of the first and second recesses r1 and r2 mayhave, for example, a slope. The first recess r1 and the second recess r2are illustrated to be empty spaces. In one embodiment, a sacrificiallayer may be filled in the first recess r1 and the second recess r2 inorder to ensure the reliability of the process.

Referring to FIG. 25C, a plurality of trenches passing through the wafer1000 may be on the bottom surfaces of the plurality of recesses,respectively. The plurality of trenches may include a first trench t1and a second trench t2. The first trench t1 may be formed on the bottomsurface of the first recess r1. The second trench t2 may be formed onthe bottom surface of the second recess r2.

When the sacrificial layer is filled in the first recess r1 and thesecond recess r2, the first trench t1 and the second trench t2 may beformed to pass through the sacrificial layer in the first recess r1 andthe second recess r2, respectively. The width of each of the pluralityof recesses may be larger than the width of each of the plurality oftrenches. For example, a width Wr of the first recess r1 may be largerthan a width Wt of the first trench t1.

Referring to FIGS. 3, 11A, and 25D, the first tape 1300 may be removedfrom the second surface 1000_2 of the wafer, thereby fabricating aplurality of semiconductor chips. The shape of each of the plurality ofsemiconductor chips may be a stepped shape. The plurality ofsemiconductor chips may include the first semiconductor chip 110 (forexample, as shown in FIG. 3) and the second semiconductor chip 210 (forexample, as shown in FIG. 11A), which have the same shape. For example,the first portion 110_1 of the first semiconductor chip may include asidewall t1_s of the first trench t1 and a sidewall t2_s of the secondtrench t2. The second portion 110_2 of the first semiconductor chip mayinclude a sidewall r1_s of the first recess r1 and a sidewall r2_s ofthe second recess r2. The first semiconductor chip 110 including thefirst to fifth portions 110_1, 110_2 and 110_3 of FIG. 19 may befabricated by further forming a third recess between the first recess r1and the second recess r2 in FIG. 25B. Then, in FIG. 25C, a trench maynot be formed on the bottom surface of the third recess.

FIGS. 26A and 26B illustrate an embodiment of a method for forming thefirst semiconductor chip 110 (for example, as shown in FIG. 3) and thesecond semiconductor chip 210 (for example, as shown in FIG. 11A). FIG.26A is a view after the steps of FIGS. 25A and 25B are performed.

Referring to FIG. 26A, after the steps of FIGS. 25A and 25B areperformed on the wafer 1000, the first tape 1300 may be removed from thesecond surface 1000_2 of the wafer. A second tape 1310 may be attachedto the first surface 1000_1 of the wafer. After the second tape 1310 isattached, a plurality of trenches including the first trench t1 and thesecond trench t2 may be formed. Referring to FIG. 26B, the second tape1310 may be removed from the first surface 1000_1 of the wafer, therebyfabricating a plurality of semiconductor chips.

FIGS. 27A to 27C illustrate an embodiment of a method for forming thefirst semiconductor chip 110 (for example, as shown in FIG. 3) and thesecond semiconductor chip 210 (for example, as shown in FIG. 11A).Referring to FIG. 27A, the wafer 1000 having a rear surface on whichgrinding has been performed may include the first surface 1000_1 and thesecond surface 1000_2 facing each other.

Referring to FIG. 27B, a part of the first surface 1000_1 of the wafermay be removed to form a plurality of recesses spaced apart from eachother. For example, it is possible to change the crystal of the wafer1000 by locally irradiating a laser beam on the first surface 1000_1 ofthe wafer. For example, in the case of a silicon wafer, a portionirradiated with the laser beam may be changed to polysilicon. A portionof the first surface 1000_1 of the wafer on which the laser beam islocally irradiated may be removed through an etching process to form aplurality of recesses. In one embodiment, boron may be locally implantedinto the first surface 1000_1 of the wafer. A portion of the firstsurface 1000 _(—) 1 of the wafer into which boron is implanted may beremoved through a selective etching process to form a plurality ofrecesses. In one embodiment, for example, a plurality of recesses may beformed by rotating the blade in the horizontal or vertical directionwith respect to the first surface 1000_1 of the wafer.

Referring to FIG. 27C, a plurality of trenches passing through the wafer1000 may be formed on the bottom surfaces of the plurality of recesses.respectively. For example, a plurality of trenches may be formed throughan etching process using the above-described laser or boronimplantation. In one embodiment, a plurality of trenches may be formedusing, for example, a laser or a sawing blade.

FIGS. 28A to 28D illustrate an embodiment of a method for fabricating asemiconductor device package including the first semiconductor chip 110formed using the process of FIGS. 25A to 25D, the process of FIGS. 26Ato 26B, or the process of FIGS. 27A to 27C.

Referring to FIG. 28A, the method for fabricating a semiconductor devicepackage according to some embodiments may include mounting the firstsemiconductor chip 110 on the first semiconductor package substrate 101.

Referring to FIG. 28B, the method for fabricating a semiconductor devicepackage according to some embodiments may include forming a pre-moldingmaterial 120 p on the first semiconductor package substrate 101 so as tosurround the sidewall of the first semiconductor chip 110. Thepre-molding material 120 p may be formed by, for example, a MoldedUnderfill (MUF) method.

Referring to FIG. 28C, the method for fabricating a semiconductor devicepackage according to some embodiments may include forming the hole 310 hin the pre-molding material 120 p to form the first molding material120. The hole 310 h may be formed by removing a part of the pre-moldingmaterial 120 p.

Referring to FIG. 28D, the method for fabricating a semiconductor devicepackage according to some embodiments may include disposing the secondportion 110_2 of the first semiconductor chip so as to overlap the firstinterposer hole 300 h_1. For example, the interposer 300 may be disposedsuch that the second portion 110_2 of the first semiconductor chip isinserted into the first interposer hole 300 h 1. Further, the interposer300 may be disposed such that the third connection element 310 isinserted into the hole 310 h. After the interposer 300 is disposed, thefirst molding material 120 may be further formed to fill the empty spacebetween the interposer 300 and the first semiconductor package substrate101.

Referring to FIG. 2A, the method for fabricating a semiconductor devicepackage according to some embodiments may include disposing anothersemiconductor package (e.g., the second semiconductor package 200) onthe interposer 300.

Referring to FIG. 29A, the method for fabricating a semiconductor devicepackage according to some embodiments may include mounting apre-semiconductor chip 110 p having no steps on the first semiconductorpackage substrate 101.

Referring to FIG. 29B, the method for fabricating a semiconductor devicepackage according to some embodiments may include forming thepre-molding material 120 p on the first semiconductor package substrate101 so as to surround the side surface of the pre-semiconductor chip 110p. The pre-molding material 120 p may be formed to fill the spacebetween the pre-semiconductor chip 110 p and the first semiconductorpackage substrate 101. The pre-molding material 120 p may expose theupper surface of the pre-semiconductor chip 110 p.

Referring to FIG. 28B, the method for fabricating a semiconductor devicepackage according to some embodiments may include forming the firstsemiconductor chip 110 by removing a part of the pre-molding material120 p and a part of the pre-semiconductor chip 110 p. For example, themethod for fabricating a semiconductor device package according to someembodiments may include removing a part of the pre-molding material 120p to reduce the height of the pre-molding material 120 p. In this case,a part of the sidewall of the pre-semiconductor chip 110 p adjacent tothe pre-molding material 120 p may also be removed. The portion wherethe sidewall of the pre-semiconductor chip 110 p adjacent to thepre-molding material 120 p is removed may be the second portion 110_2 ofthe first semiconductor chip. The portion surrounded by the pre-moldingmaterial 120 p whose height is reduced may be the first portion 110_1 ofthe first semiconductor chip.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of skill in the art as of thefiling of the present application, features, characteristics, and/orelements described in connection with a particular embodiment may beused singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwiseindicated. Accordingly, various changes in form and details may be madewithout departing from the spirit and scope of the embodiments set forthin the claims.

What is claimed is:
 1. A semiconductor device package, comprising: afirst semiconductor package including a first semiconductor packagesubstrate and a first semiconductor chip; a second semiconductor packageincluding a second semiconductor package substrate and a secondsemiconductor chip; and an interposer between the first semiconductorpackage and the second semiconductor package to electrically connect thefirst semiconductor package to the second semiconductor package, whereinthe interposer includes a first interposer hole passing through theinterposer and wherein the first semiconductor chip includes a firstportion and a second portion which protrudes from the first portion andwhich is inserted into the first interposer hole.
 2. The semiconductordevice package as claimed in claim 1, wherein: the interposer includes aconnector on the interposer, a width of the first portion is larger thana width of the second portion, and a part of the first portion overlapsthe connector.
 3. The semiconductor device package as claimed in claim1, wherein: the second semiconductor package is on the firstsemiconductor package, and the first portion is between the secondportion and the first semiconductor package substrate.
 4. Thesemiconductor device package as claimed in claim 1, wherein: the firstsemiconductor package is on the second semiconductor package, the firstsemiconductor package substrate includes a first substrate hole passingthrough the first semiconductor package substrate, the second portion isinserted into the first interposer hole through the first substratehole, and the second portion is between the first portion and the secondsemiconductor chip.
 5. The semiconductor device package as claimed inclaim 1, wherein: the second semiconductor package is on the firstsemiconductor package, the second semiconductor package substrateincludes a second substrate hole passing through at least a part of thesecond semiconductor package substrate, the second portion of the firstsemiconductor chip includes a portion to be inserted into the firstinterposer hole and a portion to be inserted into the second substratehole, and the portion to be inserted into the first interposer hole andthe portion to be inserted into the second substrate hole are betweenthe first portion and the second semiconductor chip.
 6. Thesemiconductor device package as claimed in claim 1, wherein: the secondsemiconductor package is on the first semiconductor package, the secondsemiconductor package substrate includes a second substrate hole passingthrough the second semiconductor package substrate, the secondsemiconductor chip includes a third portion and a fourth portion whichprotrudes from the third portion and is inserted into the secondsubstrate hole, a width of the third portion is larger than a width ofthe fourth portion, and the second portion is between the fourth portionand the first portion.
 7. The semiconductor device package as claimed inclaim 1, wherein: the first semiconductor package includes a thirdsemiconductor chip spaced apart from the first semiconductor chip, and apart of the third semiconductor chip is not inserted into theinterposer.
 8. The semiconductor device package as claimed in claim 7,wherein: the first semiconductor package substrate includes a firstcavity and a second cavity spaced apart from the first cavity, the firstportion is in the first cavity, the third semiconductor chip is in thesecond cavity, and a part of the third semiconductor chip is notinserted into the interposer.
 9. The semiconductor device package asclaimed in claim 1, further comprising: a third semiconductor packageincluding a third semiconductor package substrate and a fourthsemiconductor chip, the third semiconductor package shares theinterposer with the first and second semiconductor packages, and a partof the fourth semiconductor chip is not inserted into the interposer.10. The semiconductor device package as claimed in claim 1, wherein: awidth of the first portion is larger than a width of the second portion,the first semiconductor chip includes a third portion spaced apart fromthe second portion and protruding from the first portion, a width of thethird portion is less than a width of the first portion, the interposerincludes a second interposer hole spaced apart from the first interposerhole and passes through the interposer, and the third portion isinserted into the second interposer hole.
 11. A semiconductor devicepackage, comprising: a first semiconductor package including a firstsemiconductor package substrate and a first semiconductor chip includinga first portion and a second portion protruding from the first portion;a second semiconductor package including a second semiconductor packagesubstrate and a second semiconductor chip; an interposer between thefirst semiconductor package and the second semiconductor package, theinterposer including a first interposer hole exposing the secondportion, the interposer including a first surface facing a secondsurface; and a connector on the first surface of the interposer, whereina width of the first portion is larger than a width of the secondportion and wherein a part of the first portion overlaps the connector.12. The semiconductor device package as claimed in claim 11, wherein:the second semiconductor package is on the first semiconductor package,and the connector is between the first surface of the interposer and thesecond semiconductor package substrate.
 13. The semiconductor devicepackage as claimed in claim 12, wherein at least a part of the secondportion is inserted into the second semiconductor package substrate. 14.The semiconductor device package as claimed in claim 12, wherein: thesecond semiconductor chip includes a third portion and a fourth portionprotruding from the third portion, a width of the third portion islarger than a width of the fourth portion, at least a part of the fourthportion is inserted into the second semiconductor package substrate, anda part of the third portion overlaps the connector and the firstportion.
 15. The semiconductor device package as claimed in claim 11,wherein: the first semiconductor package is on the second semiconductorpackage, the first semiconductor package substrate includes a firstsubstrate hole passing through the first semiconductor packagesubstrate, the connector is between the first surface of the interposerand the first semiconductor package substrate, and the second portion isexposed through the first substrate hole and the first interposer hole.16. An apparatus, comprising: a first semiconductor package; a secondsemiconductor package; and an interposer to electrically connect thefirst semiconductor package to the second semiconductor package, whereinthe interposer includes a hole and wherein a first portion of asemiconductor chip in the first semiconductor package is in the hole andextends in a direction of the second semiconductor package.
 17. Theapparatus as claimed in claim 16, wherein the second semiconductorpackage overlaps the first semiconductor package.
 18. The apparatus asclaimed in claim 16, wherein: the semiconductor chip includes a secondportion, and the second portion of the semiconductor chip overlaps asurface of the interposer.
 19. The apparatus as claimed in claim 16,wherein the interposer includes a connector to establish electricalcontact with the first semiconductor package or the second semiconductorpackage.
 20. The apparatus as claimed in claim 16, wherein: theinterposer has a first width, the first semiconductor package has asecond width, and the second width is greater than the first width.